1. Field of the Invention
The present invention relates to a latch using a differential sense amplifier in a CMOS integrated circuit and a D-type flip-flop. More concretely, it relates to a latch mounting a differential sense amplifier using an inverter loop and a D-type flip-flop comprised using this as a master side latch and using an RS latch as a slave side latch.
2. Description of the Related Art
As one important element determining an operation frequency and/or power consumption of a CMOS VLSI, a D-type flip-flop can be mentioned.
Various procedures for raising the speed of a flip-flop and lowering the power consumption have continued to be proposed up to the present.
The D-type flip-flops announced in recent years include a D-type flip-flop referred to as a xe2x80x9csense amplifier-based flip-flopxe2x80x9d (document: J. Montanaro et al., xe2x80x9cA 160 MHz 32b 0.5 W COMS RISC Microprocessorxe2x80x9d, ISSCC Digest of Technical Papers, pp. 214-215, February 1996).
Below, this D-type flip-flop will be referred to as a xe2x80x9cdifferential sense amplifier type D-type flip-flopxe2x80x9d.
This differential sense amplifier type D-type flip-flop is one type of master/slave flip-flop comprised of a combination of a master latch and a slave latch.
The conventional master/slave flip-flop is a combination of D-type latches.
Contrary to this, a differential sense amplifier type D-type flip-flop mounts a differential sense amplifier using an inverter loop for the master side latch, mounts an RS latch for the slave side latch, and combines them to realize a D-type flip-flop.
FIG. 16 is a circuit diagram of an example of the configuration of a conventional differential sense amplifier type D-type flip-flop.
This differential sense amplifier type D-type flip-flop 1 is comprised by a master side latch 2 and a slave side latch 3 connected in cascade via nodes H and H_X as shown in FIG. 16.
The master side latch 2 has p-channel MOS (PMOS) transistors PT21 to PT24, n-channel MOS (NMOS) transistors NT21 to NT26, an inverter INV21, a synchronization signal input terminal T"PHgr", a data input terminal TD, and data output terminals TQ and T_QX.
Sources of the PMOS transistors PT21 to PT24 are connected to a supply line of a power supply voltage VDD.
Drains of the PMOS transistors PT21 and PT22 are connected to the drain of the NMOS transistor NT21, and a connection node ND21 thereof is connected to a gate of the PMOS transistor PT23, a gate of the NMOS transistor NT22, and the node H_X.
The drains of the PMOS transistors PT23 and PT24 are connected to the drain of the NMOS transistor NT22, and a connection node ND22 thereof is connected to a gate of the PMOS transistor PT22, a gate of the NMOS transistor NT21, and the node H.
Then, gates of the PMOS transistors PT21 and PT24 are connected to the synchronization signal input terminal T"PHgr".
The source of the NMOS transistor NT21 is connected to the drain of the NMOS transistor NT23, and an intermediate node F_X is comprised by the connection point thereof. The source of the NMOS transistor NT22 is connected to the drain of the NMOS transistor NT24, and an intermediate node F is comprised by the connection point thereof.
Sources of the NMOS transistor NT23 and NMOS transistor NT24 are connected to each other, and an intermediate node G is comprised by the connection point thereof. This intermediate node G is connected to the drain of the NMOS transistor NT25, and the source of the NMOS transistor NT25 is connected to a ground potential GND.
Then, the source and the drain of the NMOS transistor NT26 are connected to the nodes F and F_X.
A gate of the NMOS transistor NT23 is connected to the data input terminal TD, a gate of the NMOS transistor NT24 is connected to an output terminal of the inverter INV21, and an input terminal of the inverter INV21 is connected to the data input terminal TD. A gate of the NMOS transistor NT25 is connected to the synchronization signal input terminal T"PHgr", and a gate of the NMOS transistor NT26 is connected to the supply line of the power supply voltage VDD.
Also, the slave side latch 3 is comprised by 2-input NAND gates NA31 and NA32.
A first input terminal of the NAND gate NA31 is connected to the node H, and a second input terminal is connected to an output terminal of the NAND gate NA32 and the output terminal TQ of the output data Q.
A first input terminal of the NAND gate NA32 is connected to the node H_X, and a second input terminal is connected to an output terminal of the NAND gate NA31 and the output terminal TQ_X of the inverted output data Q_X.
Next, a detailed explanation will be made of the operation of the conventional differential sense amplifier type D-type flip-flop 1.
This flip-flop 1 fetches the value of the data input signal D in synchronization with a rising edge of the synchronization signal "PHgr" and outputs the same to the data output terminal TQ and the inverted data output terminal TQ_X. The value is held for one cycle of the synchronization signal "PHgr".
In the period where "PHgr"=0, the PMOS transistors PT21 and PT24 become ON, and the NMOS transistor NT25 becomes cut off.
FIG. 17 is a view of an equivalent circuit of the circuit of FIG. 16 in this period where "PHgr"=0 and where the data input signal D=1.
In the period where "PHgr"=0, the PMOS transistors PT21 and PT24 equivalently behave as resistors, and the nodes H and H_X are precharged to the potential of complete logic 1 through them.
Then, the PMOS transistors PT22 and PT23 become cut off. The NMOS transistors NT21 and NT22 equivalently behave as diodes since the gate terminals and the drain terminals become the same potentials.
Accordingly, when the power supply voltage is VDD [V] and the threshold value of the NMOS transistor is Vtn, the potentials of the nodes F and F_X at this time an be estimated to be (VDDxe2x88x92Vtn) [V].
When "PHgr"=0, both of the output nodes H and H_X of the master side latch 2 have the logic 1. This operates NAND-RS latch of the slave side latch 3 as the hold mode.
When "PHgr" becomes equal to 1, the PMOS transistors PT21 and PT24 become cut off, the NMOS transistor NT25 becomes ON, and the sense amplifier operates.
Either of the NMOS transistor NT23 and the NMOS transistor NT24 has become cut off according to state of the data input signal D and the inverted signal DX thereof. In the example of FIG. 17, the NMOS transistor NT24 has become cut off.
At this time, a difference is produced in conductive resistances possessed by the nodes F and F_X with respect to the ground.
A view simply considering the conductive resistances of the nodes F and F_X is shown in FIG. 18.
According to this FIG. 18, the conductive resistance possessed by the node F_X with respect to the ground becomes (r23+r25) xcexa9, and the conductive resistance of the node F becomes (r26+r23+r25) xcexa9.
Such a difference of conductive resistances appears in the discharge speed of charges on the nodes H and H_X. In this example, the conductive resistance possessed by the node F_X with respect to the ground is smaller, so the charge on the node H_X is more quickly discharged. At this time, also the charge on the node H is discharged.
However, due to the lowering of the potential of the node H_X, the PMOS transistor PT23 becomes ON and the NMOS transistor NT22 becomes cut off, and the potential of the node H which starts lower rises to obtain the potential of a complete logic 1 again.
In this way, a normal state is established in the inverter loop comprised by the PMOS transistors PT22 and PT23 and the NMOS transistors NT21 and NT22.
Thereafter, even when the data input signal D and the inverted signal DX thereof change and the transistor which becomes cut off changes from the NMOS transistor NT24 to the NMOS transistor NT23, this normal state is not destroyed.
This is because, either of the NMOS transistors NT23 and NT24 is always ON, and both of the nodes F and F_X always have paths reaching the ground via the NMOS transistor NT26, so the inverter loop is always connected to the ground.
In this way, either of the output nodes H and H_X of the master side latch 2 becomes the logic 0 when "PHgr"=1.
Upon receipt of this, the RS latch of the slave side R latch 3 is set or reset, and the value in accordance with the input data appears at the outputs Q and QX.
FIGS. 19A and 19B are views of operation waveforms obtained by circuit simulations of the flip-flop 1 of FIG. 16.
The flip-flop 1 of FIG. 16 is characterized in a small clock load because of a high speed sampling operation by the differential sense amplifier and the small number of transistors connected to the input terminal T"PHgr" of the synchronization signal "PHgr", i.e., 3 in comparison with the conventional master/slave flip-flop combining the D-latches.
However, the conventional differential sense amplifier type D-type flip-flop shown in FIG. 16 has the following problems 1, 2, and 3.
Problem 1: Problem of Speed
The operation speed of the differential sense amplifier type D-type flip-flop 1 is determined as the discharge speed of charges on the nodes H and H_X. Then, this discharge speed is determined as the conductive resistances possessed by the nodes F and F_X with respect to the ground.
Namely, for a high speed operation of this flip-flop 1, the conductive resistances of the nodes F and F_X must be small.
The resistance values r26, r23, and r25 in the equivalent circuit shown in FIG. 18 show equivalent resistance values when the NMOS transistors NT26, NT24, and NT25 become ON.
The equivalent resistance value R when the MOS transistor becomes ON is proportional to a gate length L of the transistor and inversely proportional to the gate width W.
In the general design of a CMOS VLSI logic circuit, the gate length L is fixed to the minimum value. Accordingly, the quantity which can be operated on in the design is the gate width W. In order to reduce the conductive resistances, it is necessary to enlarge the gate width W of each transistor.
However, the gate capacity C of the MOS transistor becomes large in proportion to the product of L and W. For this reason, there arises a problem in that, when the gate width W is enlarged, the gate capacity increases and the power consumption increases.
Problem 2: Problem 1 in Power
In the differential sense amplifier type D-type flip-flop 1, the number of the transistors connected to the input terminal T"PHgr" of the synchronization signal "PHgr" is 3 and small, and the clock load is small.
However, this does not always means that the power consumed for the clock can be reduced.
At the change from "PHgr"=1 to "PHgr"=0, charges are supplied to the node outputting the logic 0 between the nodes H and H_X. The nodes H and H_X are also connected to the RS latch of the slave side latch 3, so the charges are also supplied to the gate capacity possessed by the RS latch.
Also, at the change from "PHgr"=1 to "PHgr"=0, the potentials of both of the nodes F and F_X rise from 0 [V] to (VDDxe2x88x92Vtn) [V]. Also at this time, considerable charges are supplied from the power supply.
That is, although the number of the transistors connected to the input terminal T"PHgr" of the synchronization signal "PHgr" is three, the charges from the power supply are also supplied to other locations than the gate capacities possessed by these three transistors.
Accordingly, actually, the amount of charges charged or discharged in accordance with the change of the clock signal (synchronization signal) input to the input terminal T"PHgr" is large, and the power consumption does not become small.
Problem 3: Problem 2 in Power
The differential sense amplifier type D-type flip-flop 1 needs the data input signal D and the inverted signal DX thereof in its operation principle.
In the design of a general CMOS VLSI logic circuit, one bit of a data signal is transmitted by one signal line. The method of always preparing the inverted signal of the data and transmitting one bit of a data signal by two lines is technically possible, and has been already put into practical use, but its use is limited to special regions.
Accordingly, in the general case, it is necessary to use the inverter INV21 as shown in FIG. 16 and prepare the inverted signal of the data input by itself.
The maximum determining factor of the power consumption in the CMOS VLSI logic circuit is the charge and discharge of charges accompanied with a change of the node potential. That is, when the input signal changes, power is consumed.
In the case of the circuit of FIG. 16, when the data input signal D changes, power is consumed in the NMOS transistors NT23 and NT24 and the inverter INV21.
As mentioned before, a differential sense amplifier type D-type flip-flop 1 has to use an inverter for generating an inverted signal of a data input signal in its operation principle, so there is the problem that this inverter""s worth of the power consumption cannot in principle be reduced when considering reduction of the power consumption.
An object of the present invention is to provide a latch and a D-type flip-flop capable of realizing high speed operation.
Also, a second object of the present invention is to provide a latch and a D-type flip-flop capable of achieving a reduction of the power consumption.
According to a first aspect of the present invention, there is provided a latch comprising: a first output node; a second output node; a first intermediate node; a second intermediate node; a third intermediate node; an inverter loop having a first inverter provided with first and second power supply terminals and having the first power supply terminal connected to the first intermediate node and a second inverter provided with first and second power supply terminals and having the first power supply terminal connected to the second intermediate node, the output terminal of the first inverter and the input terminal of the second inverter being connected to the first output node, and the output terminal of the second inverter and the input terminal of the first inverter being connected to the second output node; a first input discriminating means containing a resistor component, electrically isolating the first intermediate node and the third intermediate node when the data input signal is at a first potential level, and connecting them when it is at a second potential level; a second input discriminating means containing a resistor component, electrically isolating the second intermediate node and the third intermediate node when an inverted signal of the data input signal is at the first potential level, and connecting them when it is at the second potential level; a first parallel resistor means connected between the first intermediate node and the third intermediate node in parallel with the first input discriminating means; a second parallel resistor means connected between the second intermediate node and the third intermediate node in parallel with the second input discriminating means; a power supply isolating means for electrically isolating the third intermediate node and a reference potential when a synchronization signal is at the first potential level and connecting them when it is at the second potential level; and a presetting means for setting the first output node and the second output node at predetermined potentials when the synchronization signal is at the first potential level.
According to a second aspect of the present invention, there is provided a latch comprising: a first output node; a second output node; a first intermediate node; a second intermediate node; a third intermediate node; an inverter loop having a first inverter provided with first and second power supply terminals and having the first power supply terminal connected to the first intermediate node and a second inverter provided with first and second power supply terminals and having the first power supply terminal connected to the second intermediate node, the output terminal of the first inverter and the input terminal of the second inverter being connected to the first output node, and the output terminal of the second inverter and the input terminal of the first inverter being connected to the second output node; a first discriminating means containing a resistor component, electrically isolating the first intermediate node and the third intermediate node when the data input signal is at the first potential level, and connecting them when it is at the second potential level; a second discriminating means containing a resistor component, electrically isolating the second intermediate node and the third intermediate node when the potential of the first output node is at the first potential level, and connecting them when it is at the second potential level; a first parallel resistor means connected between the first intermediate node and the third intermediate node in parallel with the first discriminating means; a second parallel resistor means connected between the second intermediate node and the third intermediate node in parallel with the second discriminating means; a power supply isolating means for electrically isolating the third intermediate node and the reference potential when the synchronization signal is at the first potential level and connecting them when it is at the second potential level; and a presetting means for setting the first output node and the second output node at predetermined potentials when the synchronization signal is at the first potential level.
According to a third aspect of the present invention, there is provided a D-type flip-flop comprising: a master side latch including a first output node; a second output node; a first intermediate node; a second intermediate node; a third intermediate node; an inverter loop having a first inverter provided with first and second power supply terminals and having the first power supply terminal connected to the first intermediate node and a second inverter provided with first and second power supply terminals and having the first power supply terminal connected to the second intermediate node, the output terminal of the first inverter and the input terminal of the second inverter being connected to the first output node, and the output terminal of the second inverter and the input terminal of the first inverter being connected to the second output node; a first input discriminating means containing a resistor component, electrically isolating the first intermediate node and the third intermediate node when the data input signal is at a first potential level, and connecting them when it is at a second potential level; a second input discriminating means containing a resistor component, electrically isolating the second intermediate node and the third intermediate node when an inverted signal of the data input signal is at the first potential level, and connecting them when it is at the second potential level; a first parallel resistor means connected between the first intermediate node and the third intermediate node in parallel with the first input discriminating means; a second parallel resistor means connected between the second intermediate node and the third intermediate node in parallel with the second input discriminating means; a power supply isolating means for electrically isolating the third intermediate node and a reference potential when a synchronization signal is at the first potential level and connecting them when it is at the second potential level; and a presetting means for setting the first output node and the second output node at predetermined potentials when the synchronization signal is at the first potential level and a slave side latch having a set terminal and a reset terminal connected to either of the first output node or the second output node of the master side latch and holding the logic output of the master side latch for one cycle of the synchronization signal.
According to a fourth aspect of the present invention, there is provided a D-type flip-flop comprising: a master side latch including a first output node; a second output node; a first intermediate node; a second intermediate node; a third intermediate node; an inverter loop having a first inverter provided with first and second power supply terminals and having the first power supply terminal connected to the first intermediate node and a second inverter provided with first and second power supply terminals and having the first power supply terminal connected to the second intermediate node, the output terminal of the first inverter and the input terminal of the second inverter being connected to the first output node, and the output terminal of the second inverter and the input terminal of the first inverter being connected to the second output node; a first discriminating means containing a resistor component, electrically isolating the first intermediate node and the third intermediate node when the data input signal is at the first potential level, and connecting them when it is at the second potential level; a second discriminating means containing a resistor component, electrically isolating the second intermediate node and the third intermediate node when the potential of the first output node is at the first potential level, and connecting them when it is at the second potential level; a first parallel resistor means connected between the first intermediate node and the third intermediate node in parallel with the first discriminating means; a second parallel resistor means connected between the second intermediate node and the third intermediate node in parallel with the second discriminating means; a power supply isolating means for electrically isolating the third intermediate node and the reference potential when the synchronization signal is at the first potential level and connecting them when it is at the second potential level; and a presetting means for setting the first output node and the second output node at predetermined potentials when the synchronization signal is at the first potential level and a slave side latch having a set terminal and the reset terminal connected to either of the first output node or the second output node of the master side latch and holding the logic output of the master side latch for one cycle of the synchronization signal.
Further, in the present invention, the presetting means includes a balancing means for electrically connecting the first output node and the second output node when the synchronization signal is at the first potential level and isolating them when it at the second potential level.
According to the present invention, the first parallel resistor means is connected between the first intermediate node and the third intermediate node in parallel with the first input discriminating means receiving the data input signal, and the second parallel resistor means is connected between the second intermediate node and the third intermediate node in parallel with the second input discriminating means receiving the inverted signal of the data input signal.
By this, the equivalent combined resistance of the discharge paths becomes small due to the first and second parallel resistor means.
As a result, high speed operation becomes possible.
Also, according to the present invention, initialization potentials of internal first and second intermediate nodes are lowered by the balancing means.
As a result, the power consumption is reduced.
Also, according to the present invention, the first parallel resistor means is connected between the first intermediate node and the third intermediate node in parallel with the first discriminating means receiving the data input signal, and the second parallel resistor means is connected between the second intermediate node and the third intermediate node in parallel with the second input discriminating means receiving the potential of the first output node.
Also, according to the present invention, initialization potentials of internal first and second intermediate nodes are lowered by the balancing means.
As a result, the power consumption is reduced.